Electromigration Modeling at Circuit Layout Level

Highlights a new method which models the interconnects EM reliability in both 3D and circuit layout level. Combines Cadence and ANSYS softwares to model interconnect reliability of real 3D circuit made up of complete interconnect structures and surrounding materials. Compares the circuit EM lifetime with different interconnect structures, surrounding materials, circuit layout and process variations.

Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels. Electromigration (EM) of interconnects has now become the dominant failure mechanism that determines the circuit reliability. This brief addresses the readers to the necessity of 3D real circuit modelling in order to evaluate the EM of interconnect system in ICs, and how they can create such models for their own applications. A 3-dimensional (3D) electro-thermo-structural model as opposed to the conventional current density based 2-dimensional (2D) models is presented at circuit-layout level.

https://www.springer.com/gp/book/9789814451208

 

回到頂端