Modeling and analysis of gate-all-around silicon nanowire FET

Xiangchen Chen and Cher Ming Tan, “Modeling and analysis of gate-all-around silicon nanowire FET,” Microelectronics Reliability, Volume 54, Issues 6–7, Pages 1103–1108, June–July 2014.
https://www.sciencedirect.com/science/article/pii/S0026271413004472

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